Description of Individual Course Units
Course Unit CodeCourse Unit TitleType of Course UnitYear of StudySemesterNumber of ECTS Credits
9105056011998Advanced Computer ArchitectureCompulsory118
Level of Course Unit
Third Cycle
Objectives of the Course
Aim of this course is to comprehend how programs written with high level language works on computer hardware, to comprehend computer organization and performance analysis, to comprehend state of the art developments about computer architecture.
Name of Lecturer(s)
Asst.Prof. Dr.Cengiz Güngör
Learning Outcomes
1To be able to write machine level programs using MIPS command set and to read programs which were wiritten with tihs language.
2To be able to use SPIM simulator.
3To be able to comprehend interrupts, ISA and performance.
4To be able to comprehend operation of single cycle data path and pipeline.
5To be able to draw pipelined data path and to comprehend Forwarding.
6To be able to comprehend pipeline stalings and intel Asm.
7To be able to comprehend SSE, MMX and caches.
8To be able to comprehend structures and operation principles of virtual memories, parallel programs and OpenMP.
9To be able to comprehend Input/Output devices and shared memories.
10To be able to comprehend instruction level parallelism and to use it written programs.
11To be able to comprehend scheduling.
Mode of Delivery
Face to Face
Prerequisites and co-requisities
None
Recommended Optional Programme Components
To understand the lectures better, Computer Organization and Machine Language courses should be taken previously.
Course Contents
Basic principles of computer architecture. Design and organization of computer architecture. Running of programs written with high level languages on computer hardware. Using of SPIM simulator. Interrupts, ISA and performance metrics. Single cycle data path, pipeline, pipelined data path and forwarding. Pipeline stallings and Intel Asm. SSE, MMX, caches, virtual memories, parallel programs and OpenMP. I/O, shared memories and instruction level parallelism. Scheduling.
Weekly Detailed Course Contents
WeekTheoreticalPracticeLaboratory
1IntroductionReading [ Course book 1. Chapter ]
2Functions and ProgrammingReading [ Course book 2. Chapter ]
3Interrupts, ISA and PerformanceReading [ Course book 2. And 4. Chapter ]
4Single Cycle Data Path and PipelineReading [Course book 5. Chapter] Investigation of SPIM simulator
5Pipelined Data Path and ForwardingReading [Course book 6. Chapter]
6Pipeline Stallings and Intel AsmReading [Course book 6. Chapter]
7SSE, MMX and CachesReading [Course book 7. Chapter]
8Caches (Cont.)Reading [Course book 7. Chapter]
9Virtual Memory, Parallel Programs and OpenMPReading [Course book 9. Chapter]
10IO and Shared MemoryReading [Course book 8. Chapter]
11Shared Memory (Cont.) and Instruction Level ParallelismSolution of previous exams
12Midterm
13Scheduling
14Summary and Studying for Final ExamSolution of Previous Final Exams
Recommended or Required Reading
COURSE BOOKS : 1. Hannessy, J. L. , Patterson, D. A., Computer Architecture: A Quantitative Approach, 3rd edition, Morgan Kaufman Pub. Inc., 1996. 2. Patterson, D. A., Hennessy, J. L., Computer Organization and Design, The Hardware/Software Interface, 3rd edition, The Morgan Kaufmann Series, 2007.
Planned Learning Activities and Teaching Methods
Assessment Methods and Criteria
Term (or Year) Learning ActivitiesQuantityWeight
SUM0
End Of Term (or Year) Learning ActivitiesQuantityWeight
SUM0
SUM0
Language of Instruction
Turkish
Work Placement(s)
None
Workload Calculation
ActivitiesNumberTime (hours)Total Work Load (hours)
Midterm Examination122
Final Examination122
Attending Lectures13339
Practice155
Project Preparation12020
Project Presentation155
Individual Study for Mid term Examination12020
Individual Study for Final Examination13030
Reading10770
Homework31545
TOTAL WORKLOAD (hours)238
Contribution of Learning Outcomes to Programme Outcomes
PO
1
PO
2
PO
3
PO
4
PO
5
PO
6
PO
7
PO
8
PO
9
PO
10
PO
11
PO
12
PO
13
PO
14
PO
15
PO
16
PO
17
PO
18
PO
19
PO
20
PO
21
PO
22
PO
23
PO
24
LO1                        
LO2                        
LO3                        
LO4                        
LO5                        
LO6                        
LO7                        
LO8                        
LO9                        
LO1055   4        44 3      
LO1155             4        
* Contribution Level : 1 Very low 2 Low 3 Medium 4 High 5 Very High
 
Ege University, Bornova - İzmir / TURKEY • Phone: +90 232 311 10 10 • e-mail: intrec@mail.ege.edu.tr